Design of Low- Power High-Speed 32-Bit Truncation-Error-Tolerant Adder
by Maneesha (V.P)
Additional authors:
Ramprakash (K)
Year: 2011
| Item type | Current location | Call number | Status | Notes | Date due | Barcode |
|---|---|---|---|---|---|---|
| Project | Kumaraguru College of Technology | Available | ECE | P 3476 |
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