Memory Efficient Three Level 2-D DWT Architecture
by "Abinaya (M), Bharathi (M), Dhanashree (S), Kiruthega (S)"
Additional authors:
Nagarathinam (S)
Year: 2015
Online resources:
| Item type | Current location | Call number | Status | Notes | Date due | Barcode |
|---|---|---|---|---|---|---|
| Project | Kumaraguru College of Technology | Available | ECE | P 4510 |
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