"Verilog Digital System Design:RT Level Synthesis, Testbench and Verification"
by Navabi (Zainalabedin)
Edition statement:2 ISBN:978-0-07-025221-9.
Subject(s):
Verilog Digital System
Year: 2008
| Item type | Current location | Call number | Status | Notes | Date due | Barcode |
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Books
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Kumaraguru College of Technology | 681.3.23.413 NAV (Browse shelf) | Available | EEE | 48779 |
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| 681.3.23.413 LIN Digital System Designs and Practices: Using Verilog HDL And FPGAs | 681.3.23.413 LIN Digital System Designs and Practices: Using Verilog HDL And FPGAs | 681.3.23.413 NAV Vhdl Analysis And Modeling Of Digital Systems | 681.3.23.413 NAV "Verilog Digital System Design:RT Level Synthesis, Testbench and Verification" | 681.3.23.413 NAV Verilog Digital System Design: RT Level Synthesis, Testbench and Verification | 681.3.23.413 NAV VHDL: Modular Design and Synthesis of Cores and Systems | 681.3.23.413 NAV VHDL: Modular Design and Synthesis of Cores and Systems |
22.5
Verilog Digital System
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