<![CDATA[Mahatma Gandhi Central LIbrary Search for 'au:"Jagadish Kumar (R), Dinesh (S), Suresh (K)"']]>

<![CDATA[Mahatma Gandhi Central LIbrary Search for 'au:"Jagadish Kumar (R), Dinesh (S), Suresh (K)"']]> http://www.library.kct.ac.in/cgi-bin/koha/opac-search.pl?q=ccl=au%3A%22Jagadish%20Kumar%20%28R%29%2C%20Dinesh%20%28S%29%2C%20Suresh%20%28K%29%22&format=rss2 2 0 50 Design of an FPGA Logic Element for Implementing a Synchronous Null Convention Logic Circuits ISBN http://www.library.kct.ac.in/cgi-bin/koha/opac-detail.pl?biblionumber=110063 By "Jagadish Kumar (R), Dinesh (S), Suresh (K)". 2008

Place Hold on Design of an FPGA Logic Element for Implementing a Synchronous Null Convention Logic Circuits

]]> http://www.library.kct.ac.in/cgi-bin/koha/opac-detail.pl?biblionumber=110063 Design of an FPGA Logic Element for Implementing a Synchronous Null Convention Logic Circuits ISBN http://www.library.kct.ac.in/cgi-bin/koha/opac-detail.pl?biblionumber=172615 By "Jagadish Kumar (R), Dinesh (S), Suresh (K)". 2008

Place Hold on Design of an FPGA Logic Element for Implementing a Synchronous Null Convention Logic Circuits

]]> http://www.library.kct.ac.in/cgi-bin/koha/opac-detail.pl?biblionumber=172615