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Design and Simulation of Control of Automation using Verilog HDL (Record no. 175223)

MARC details
000 -LEADER
fixed length control field	00428nam a2200121Ia 4500
100 ## - MAIN ENTRY--AUTHOR NAME
Personal name	"Lakshmikanth Arun (A), Pradeep (P), Rukmani (A), Sharmila (D)"
245 #0 - TITLE STATEMENT
Title	Design and Simulation of Control of Automation using Verilog HDL
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Year of publication	2001
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name	Karthik (S)
856 ## - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier	http://library.kct.ac.in/opac-tmpl/bootstrap/THESIS/523LAKSHMIKANTHARUN.pdf
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type	Project

Holdings
Withdrawn status	Home library	Current library	Shelving location	Date acquired	Accession Number	Koha item type
	Kumaraguru College of Technology	Kumaraguru College of Technology		2019-08-16	P 523	Project