000 00480nam a2200217Ia 4500
008 181205s9999 xx 000 0 und d
082 _a681.3.23.413 PAL
100 _aPalnitkar (Samir)
100 _eAUTHOR
245 0 _aVerilog HDL: a Guide to Digital Design and Synthesis
260 _c2007
300 _bCD(BOOK)
300 _ePaper Pack
300 _gNO
365 _b0
365 _b0
365 _d1
505 _a44926
942 _cNON BK
999 _c103638
_d103638