000 00411nam a2200121Ia 4500
008 190816s9999 xx 000 0 und d
100 _a"Kavitha (S), Saranya (P), Vanikiruthika (D)"
245 0 _aDesign and Implementation of HDLC Procedures Based on FPGA
260 _c2010
700 _aRajeswari Mariappan
856 _uhttp://library.kct.ac.in/opac-tmpl/bootstrap/THESIS/71206106023KAVITHA.pdf
942 _cPR
999 _c173377
_d173377