000 00395nam a2200121Ia 4500
008 190816s9999 xx 000 0 und d
100 _aDiviya (GU)
245 0 _aValidation of Test Sets for Improving the Stuck of Fault Coverage of RTL Circuits
260 _c2011
700 _aNagarathinam (S)
856 _uhttp://library.kct.ac.in/opac-tmpl/bootstrap/THESIS/0920106005DIVIYA.pdf
942 _cPR
999 _c173832
_d173832