000 00387nam a2200121Ia 4500
008 190816s9999 xx 000 0 und d
100 _aSri Ram (K)
245 0 _aMultilevel Computing Architecture for Parallelism on FPGA Using VHDL
260 _c2011
700 _aAlagu Meenaakshi (M)
856 _uhttp://library.kct.ac.in/opac-tmpl/bootstrap/THESIS/0920106015SRIRRAM.pdf
942 _cPR
999 _c173842
_d173842