000 00400nam a2200121Ia 4500
008 190816s9999 xx 000 0 und d
100 _aManojkumar M
245 0 _aDesign and FPGA Implementation of a Reconfigurable Channelization Architecture for SDR Application
260 _c2017
700 _aGovindaraju S
856 _uhttp://library.kct.ac.in/opac-tmpl/bootstrap/THESIS/P 4616.pdf
942 _cPR
999 _c175123
_d175123