000 00428nam a2200121Ia 4500
008 190816s9999 xx 000 0 und d
100 _a"Lakshmikanth Arun (A), Pradeep (P), Rukmani (A), Sharmila (D)"
245 0 _aDesign and Simulation of Control of Automation using Verilog HDL
260 _c2001
700 _aKarthik (S)
856 _uhttp://library.kct.ac.in/opac-tmpl/bootstrap/THESIS/523LAKSHMIKANTHARUN.pdf
942 _cPR
999 _c175223
_d175223