Design of an FPGA Logic Element for Implementing a Synchronous Null Convention Logic Circuits
by "Jagadish Kumar (R), Dinesh (S), Suresh (K)"
Additional authors:
Sudha (M)
Year: 2008
| Item type | Current location | Call number | Status | Notes | Date due | Barcode |
|---|---|---|---|---|---|---|
| Project | Kumaraguru College of Technology | Available | EEE | P 2358 |
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